The super instruction processor parallel design pattern for data …

Short Description
A design pattern is considered in which a distributed memory, … In the design pattern, we consider the elementary data item for a modern parallel …

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Content
Workshop on Patterns in HPC
1
The super instruction processor parallel design
pattern for data and floating point intensive
algorithms
V. Lotrich, M. Ponton, L. Wang, A. Yau, N. Flocke, A. Perera, E. Deumens, R. Bartlett
AcesQC, Gainesville, Florida
ABSTRACT
A design pattern is considered in which a distributed memory, multi processor computer
is viewed as an early generation processor. In such processors, each instruction operates
on individual floating point numbers and consumes a variable yet significant number of
cycles. In the design pattern, we consider the elementary data item for a modern parallel
computer to be a block of many numbers. Each operation involves a significant amount
of CPU work, since the operands and result are blocks. We also consider memory access
operations to include the delays incurred sending blocks to remote nodes. By making all
delays explicit and organizing the algorithm such as to provide sufficient work to make
each operation take a measurable amount of time, a new paradigm for designing and
optimizing data and floating point intensive algorithms emerges. The application of the
design pattern to the construction of a parallel implementation of the Coupled Cluster
Singles and Doubles energy and gradient calculation is discussed. The…